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.TH EDIF2QMASM 1 "2019-03-27" "1.1" ""
.SH NAME
edif2qmasm \- convert EDIF netlists to QMASM source files
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.SH SYNOPSIS
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\fBedif2qmasm\fP [\-o \fIoutfile.qmasm\fP] [\-\-cycles=\fIN\fP] \fIinfile.edif\fP
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.SH DESCRIPTION
.sp
\fBediff2qmasm\fP converts a hardware circuit specified as an EDIF
netlist to a symbolic Hamiltonian suitable for running on a D\-Wave
quantum annealer using QMASM.
.sp
Typical usage is to define a circuit using a hardware\-description
language (HDL) such as Verilog then passing this to a synthesis tool
like \fByosys\fP to compile the HDL code to EDIF format.  \fBedif2qmasm\fP
can then be run on the result, and the resulting QMASM code can be fed
to \fBqmasm\fP for execution on a D\-Wave system:
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.sp
.nf
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edif2qmasm \-o something.qmasm something.edif
qmasm \-\-run something.qmasm
.ft P
.fi
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.sp
Optionally, these steps can be combined into a single shell pipeline:
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edif2qmasm something.edif | qmasm \-\-run
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.SH OPTIONS
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.TP
.B \fB\-o\fP \fIfile.qmasm\fP, \fB\-\-output=\fP\fIfile.qmasm\fP
Specify the name of the QMASM file to generate.  The default is to
write QMASM code to the standard output device.
.TP
.B \fB\-\-cycles=\fP\fIN\fP
Replicate the entire circuit \fIN\fP times.  This is used to support
sequential logic, which needs to be statically unrolled once per
cycle for QMASM execution.
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.SH NOTES
.sp
The following is an example of an interactive \fByosys\fP session that
compiles a Verilog source file, \fImycircuit.v\fP to an EDIF netlist,
\fImycircuit.edif\fP:
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yosys> read_verilog mycircuit.v
yosys> hierarchy; proc; opt; fsm; opt; techmap; opt; clean
yosys> write_edif mycircuit.edif
.ft P
.fi
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.sp
For convenience, one might want to create a script, say \fIsynth.ys\fP,
with contents like the following:
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###############################################################
# Generic synthesis script derived from the Yosys README file #
#                                                             #
# Usage: yosys infile.v synth.ys \-b edif \-o outfile.edif      #
###############################################################

# Check design hierarchy.
hierarchy

# Translate processes.
proc; opt

# Detect and optimize FSM encodings.
fsm; opt

# Convert to gate logic.
techmap; opt

# Clean up.
clean
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.fi
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.sp
This can then be run conveniently from the command line:
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.sp
.nf
.ft C
yosys mycircuit.v synth.ys \-b edif \-o mycircuit.edif
.ft P
.fi
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.SH SEE ALSO
.sp
yosys(1),
\fI\%the QMASM wiki\fP,
\fI\%Wikipedia\(aqs entry on Verilog\fP,
\fI\%Wikipedia\(aqs entry on VHDL\fP,
\fI\%Wikipedia\(aqs entry on EDIF\fP,
\fI\%D\-Wave\(aqs home page\fP
.SH AUTHOR
pakin@lanl.gov
.SH COPYRIGHT
BSD
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